There is a continual drive to increase the speed of processor systems and their ability to handle larger amounts of data. Parallelism is increasing being used in pursuit of this drive to increase speed, whereby a complex program is executed as a plurality of less complex routines run at the same time to improve performance. Another tool (that is used to increase speed is the provision of cache memories.
A cache memory works by storing copies of frequently used portions of data and instructions from the main system memory in a closely coupled, low latency cache memory. This means that data or instructions that are accessed at frequent intervals are taken from the cache memory, thereby avoiding the need to access the main system memory. Thus, as each new read and write command is issued, the system looks to the cache memory first to determine if the information is stored in the cache. If the information is available in the cache memory, access to the main system memory is not required and the command may be processed or data accessed much more readily.
Inherent in a cache memory system is a need to guarantee coherency between the data copy in one or more processor caches and the main system memory itself. One method of ensuring coherency is the “MESI” protocol, which includes state information for every cache block. The state information includes indicating whether the cache line is Modified, Shared, Exclusive and Invalid (MESI).
In a MESI system, when an unshared cache line is accessed it is marked exclusive (E). A subsequent read does not change the state, but a subsequent write to the cache line changes the state to modified (M). If another processor in the multi-processor system loads the cache data into its own cache, the cache line is marked as shared (S). If a processor wishes to write data to a shared cache, an invalidate command must be sent to all other processors, or at least to all other processors having a copy of the shared data. Before a processor can load data from a modified cache line the processor having the modified cache line must write the data back to memory and mark the data as being shared (S). Any read or write to a cache line that is marked invalid (I) results in a cache miss.
Protocols such as the MESI protocol described above ensure that cache memories are kept coherent, which makes them transparent for software in a multiprocessor system. Further details on cache memories and cache memory coherency can be found in the publication Computer Architecture a Quantitative Approach, Third Edition, John L. Hennessy and David A. Patterson, 2003.
Although cache memories offer the advantages mentioned above, they have the disadvantage of being complicated to design, and tend to be relatively expensive compared to other types of memory devices. For example, cache memories require comparators to check tags against the presented address, and selectors to select the way that matches. Cache memories also have Least Recently Used (LRU) bits for managing replacement of data, and require copyback functionality to manage write backs of modified data. Cache memories also tend to consume more power than other types of memory because of the way that bits are accessed in a cache memory. Furthermore, the manner in which data will either hit or miss in the cache depends on the replacement policy (typically LRU), which is difficult to predict for software.
Processor systems, for example processors used for digital signal processing, also use local memory as a means of increasing processing speed. A local memory allows read and/or write operations to be made directly between the processor and the local memory, rather than with a separate main memory, for example a random access memory (RAM). While a local memory allows processing speed to be increased in terms of the particular processor that has access to the local memory, it does not contribute any further advantages to a multi-processor system.
The aim of the present invention is to provide a multi processor system in which coherent caching of local memory data is provided.